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1. general description the lpc1759/58/56/54/52/51 are arm cort ex-m3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. the arm cortex-m3 is a next generation core that offe rs system enhancements such as enhanced debug features and a higher level of support block integration. the lpc1758/56/57/54/52/51 operate at cpu frequencies of up to 100 mhz. the lpc1759 operates at cpu frequencies of up to 120 mhz. the arm cortex-m3 cpu incorporates a 3-stage pipeline and uses a harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. the arm cortex-m3 cpu also includes an internal prefetch un it that supports speculative branching. the peripheral complement of the lpc1759/58/56/54/52/51 includes up to 512 kb of flash memory, up to 64 kb of data memory, ether net mac, usb device/host/otg interface, 8-channel general purpose dm a controller, 4 uarts, 2 ca n channels, 2 ssp controllers, spi interface, 2 i 2 c-bus interfaces, 2-input plus 2-output i 2 s-bus interface, 6 channel 12-bit adc, 10-bit dac, motor control pwm, quadrature encoder interface, 4 general purpose timers, 6-output general purpose pwm, ultra-low power real-time clock (rtc) with separate battery supply, and up to 52 general purpose i/o pins. 2. features and benefits ? arm cortex-m3 processor, running at frequencies of up to 100 mhz (lpc1758/56/57/54/52/51) or of up to 120 mhz (lpc1759). a memory protection unit (mpu) supporting eight regions is included. ? arm cortex-m3 built-in nested vector ed interrupt controller (nvic). ? up to 512 kb on-chip flash programming memory. enhanced flash memory accelerator enables high-speed 120 mhz operation with zero wait states. ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. ? on-chip sram includes: ? up to 32 kb of sram on the cpu with local code/data bus for high-performance cpu access. ? two/one 16 kb sram blocks with separate access paths for higher throughput. these sram blocks may be used for ethernet (lpc1758 only), usb, and dma memory, as well as for general purpose cpu instruction and data storage. ? eight channel general purpose dma controller (gpdma) on the ahb multilayer matrix that can be used with the ssp, i 2 s-bus, uart, the analog-to-digital and digital-to-analog converter peripherals, timer match signals, and for memory-to-memory transfers. lpc1759/58/56/54/52/51 32-bit arm cortex-m3 mcu; up to 512 kb flash and 64 kb sram with ethernet, usb 2. 0 host/device/otg, can rev. 7 ? 29 march 2011 product data sheet
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 2 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller ? multilayer ahb matrix interconnect prov ides a separate bus for each ahb master. ahb masters include the cpu, general purpose dma controller, ethernet mac (lpc1758 only), and the usb interface. this interconnect provides communication with no arbitration delays. ? split apb bus allows high throughput with few stalls between the cpu and dma. ? serial interfaces: ? on the lpc1758 only, ethernet mac with rmii interface and dedicated dma controller. ? usb 2.0 full-speed device/host/otg controller with dedicated dma controller and on-chip phy for device, host, and otg fu nctions. the lpc1752/51 include a usb device controller only. ? four uarts with fractional baud rate generation, internal fifo, and dma support. one uart has modem control i/o and rs-485/eia-485 support, and one uart has irda support. ? can 2.0b controller with two (lpc1759/58/56) or one (lpc1754/52/51) channels. ? spi controller with synchronous, seri al, full duplex communication and programmable data length. ? two ssp controllers with fifo and multi-protocol capab ilities. the ssp interfaces can be used with the gpdma controller. ? two i 2 c-bus interfaces supporting fast mode with a data rate of 400 kbit/s with multiple address recognition and monitor mode. ? on the lpc1759/58/56 only, i 2 s (inter-ic sound) interface for digital audio input or output, with fractional rate control. the i 2 s-bus interface can be used with the gpdma. the i 2 s-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output. ? other peripherals: ? 52 general purpose i/o (gpio) pins with configurable pull-up/down resistors. all gpios support a new, configurable open-drain operating mode. the gpio block is accessed through the ahb multilayer bus fo r fast access and located in memory such that it supports cortex-m3 bit banding and use by the general purpose dma controller. ? 12-bit analog-to-digital converter (adc) with input multiplexing among six pins, conversion rates up to 200 khz, and multiple result registers. the 12-bit adc can be used with the gpdma controller. ? on the lpc1759/58/56/54 only, 10-bit digital-to-analog converter (dac) with dedicated conversion timer and dma support. ? four general purpose timers/counters, with a total of three capture inputs and ten compare outputs. each timer block has an external count input. specific timer events can be selected to generate dma requests. ? one motor control pwm with suppor t for three-phase motor control. ? quadrature encoder interfac e that can monitor one external quadrature encoder. ? one standard pwm/timer block with external count input. ? real-time clock (rtc) with a separate power domain and dedicated rtc oscillator. the rtc block includes 20 byte s of battery-power ed backup registers. ? watchdog timer (wdt). the wdt can be cl ocked from the internal rc oscillator, the rtc oscillator, or the apb clock. ? arm cortex-m3 system tick timer, including an external clock input option.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 3 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller ? repetitive interrupt timer (rit) provides programmable and repeating timed interrupts. ? each peripheral has it s own clock divider for further power savings. ? standard jtag test/debug interface for compatibility with existing tools. serial wire debug and serial wire trace port options. ? emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution. ? integrated pmu (power management unit) automatically adjusts internal regulators to minimize power consumption during slee p, deep sleep, power-down, and deep power-down modes. ? four reduced power modes: sleep, deep-sleep, power-down, and deep power-down. ? single 3.3 v power supply (2.4 v to 3.6 v). ? one external interrupt input configurable as ed ge/level sensitive. all pins on port 0 and port 2 can be used as edge sensitive interrupt sources. ? non-maskable inte rrupt (nmi) input. ? the wakeup interrupt controlle r (wic) allows the cpu to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, power-down, and deep power-down modes. ? processor wake-up from power-down mode via any interrupt able to operate during power-down mode (includes external interrupts, rtc interrupt, usb activity, ethernet wake-up interrupt (lpc1758 only), can bus activity, port 0/2 pin interrupt, and nmi). ? brownout detect with separate threshold for interrupt and forced reset. ? power-on reset (por). ? crystal oscillator with an operating range of 1 mhz to 25 mhz. ? 4 mhz internal rc oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. ? pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from the main oscillator, the internal rc oscillator, or the rtc oscillator. ? usb pll for added flexibility. ? code read protection (crp) with different security levels. ? unique device serial number for identification purposes. ? available as 80-pin lqfp package (12 mm ? 12 mm ? 1.4 mm). 3. applications ? emetering ? lighting ? industrial networking ? alarm systems ? white goods ? motor control
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 4 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 4. ordering information 4.1 ordering options table 1. ordering information type number package name description version lpc1759fbd80 lqfp80 plastic low-profile quad package; 80 leads; body 12 ? 12 ? 1.4 mm sot315-1 lpc1758fbd80 lqfp80 plastic low-profile quad package; 80 leads; body 12 ? 12 ? 1.4 mm sot315-1 lpc1756fbd80 lqfp80 plastic low-profile quad package; 80 leads; body 12 ? 12 ? 1.4 mm sot315-1 lpc1754fbd80 lqfp80 plastic low-profile quad package; 80 leads; body 12 ? 12 ? 1.4 mm sot315-1 lpc1752fbd80 lqfp80 plastic low-profile quad package; 80 leads; body 12 ? 12 ? 1.4 mm sot315-1 LPC1751FBD80 lqfp80 plastic low-profile quad package; 80 leads; body 12 ? 12 ? 1.4 mm sot315-1 table 2. ordering options type number flash sram in kb ethernet usb can i 2 s-bus dac maximum cpu operating frequency cpu ahb sram0 ahb sram1 total lpc1759fbd80 512 kb 32 16 16 64 no device/host/otg 2 yes yes 120 mhz lpc1758fbd80 512 kb 32 16 16 64 yes device/host/otg 2 yes yes 100 mhz lpc1756fbd80 256 kb 16 16 - 32 no device/host/otg 2 yes yes 100 mhz lpc1754fbd80 128 kb 16 16 - 32 no device/host/otg 1 no yes 100 mhz lpc1752fbd80 64 kb 16 - - 16 no device only 1 no no 100 mhz LPC1751FBD80 32 kb 8 - - 8 no device only 1 no no 100 mhz
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 5 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 5. block diagram grey-shaded blocks represent periphera ls with connection to the gpdma. fig 1. block diagram sram 64/32/ 16/8 kb arm cortex-m3 test/debug interface emulation trace module flash accelerator flash 512/256/128/64/32 kb dma controller ethernet controller with dma (2) usb host/ device/otg controller with dma (4) i-code bus d-code bus system bus ahb to apb bridge 0 high-speed gpio ahb to apb bridge 1 clock generation, power control, system functions xtal1 xtal2 reset clocks and controls jtag interface debug port usb phy ssp0 uart2/3 i2s (1) ri timer system control ssp1 uart0/1 can1/can2 (1) i2c1 spi0 timer 0/1 wdt pwm1 12-bit adc pin connect gpio interrupt control rtc backup registers 32 khz oscillator apb slave group 1 apb slave group 0 rtc power domain lpc1759/58/56/54/52/51 master master master 002aae153 slave slave slave slave rom slave slave multilayer ahb matrix p0, p1, p2, p4 sck0 ssel0 miso0 mosi0 sck1 ssel1 miso1 mosi1 rxd2/3 txd2/3 scl2 i2c2 sda2 motor control pwm mcoa[2:0] mcob[2:0] mci[2:0] timer2/3 4 mat2 2 mat3 i2srx_sda i2stx_clk i2stx_ws i2stx_sda tx_mclk rx_mclk dac (3) aout quadrature encoder pha, phb index rtcx1 rtcx2 vbat pwm1[6:1] 2 mat0/1 1 cap0, 2 cap1 rd1/2 td1/2 sda1 scl1 ad0[7:2] sck/ssel mosi/miso 8 uart1 rxd0/txd0 p0, p2 pcap1[1:0] rmii pins usb pins mpu (1) lpc1759/58/56 only (2) lpc1758 only external interrupts eint0 (3) lpc1759/58/56/54 only (4) lpc1752/51 usb device only
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 6 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration lqfp80 package 60 21 40 80 61 41 1 20 002aae158 table 3. pin description symbol pin type description p0[0] to p0[31] i/o port 0: port 0 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 0 pins depends upon the pin function selected via the pin connect block. some port pins are not available on the lqfp80 package. p0[0]/rd1/txd3/ sda1 37 [1] i/o p0[0] ? general purpose digital input/output pin. i rd1 ? can1 receiver input. o txd3 ? transmitter output for uart3. i/o sda1 ? i 2 c1 data input/output (this is not an i 2 c-bus compliant open-drain pin). p0[1]/td1/rxd3/ scl1 38 [1] i/o p0[1] ? general purpose digital input/output pin. o td1 ? can1 transmitter output. i rxd3 ? receiver input for uart3. i/o scl1 ? i 2 c1 clock input/output (this is not an i 2 c-bus compliant open-drain pin). p0[2]/txd0/ad0[7] 79 [2] i/o p0[2] ? general purpose digital input/output pin. o txd0 ? transmitter output for uart0. i ad0[7] ? a/d converter 0, input 7. p0[3]/rxd0/ad0[6] 80 [2] i/o p0[3] ? general purpose digital input/output pin. i rxd0 ? receiver input for uart0. i ad0[6] ? a/d converter 0, input 6. p0[6]/ i2srx_sda/ ssel1/mat2[0] 64 [1] i/o p0[6] ? general purpose digital input/output pin. i/o i2srx_sda ? receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . (lpc1759/58/56 only). i/o ssel1 ? slave select for ssp1. o mat2[0] ? match output for timer 2, channel 0.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 7 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller p0[7]/i2stx_clk/ sck1/mat2[1] 63 [1] i/o p0[7] ? general purpose digital input/output pin. i/o i2stx_clk ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . (lpc1759/58/56 only). i/o sck1 ? serial clock for ssp1. o mat2[1] ? match output for timer 2, channel 1. p0[8]/i2stx_ws/ miso1/mat2[2] 62 [1] i/o p0[8] ? general purpose digital input/output pin. i/o i2stx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . (lpc1759/58/56 only). i/o miso1 ? master in slave out for ssp1. o mat2[2] ? match output for timer 2, channel 2. p0[9]/i2stx_sda/ mosi1/mat2[3] 61 [1] i/o p0[9] ? general purpose digital input/output pin. i/o i2stx_sda ? transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . (lpc1759/58/56 only). i/o mosi1 ? master out slave in for ssp1. o mat2[3] ? match output for timer 2, channel 3. p0[10]/txd2/ sda2/mat3[0] 39 [1] i/o p0[10] ? general purpose digital input/output pin. o txd2 ? transmitter output for uart2. i/o sda2 ? i 2 c2 data input/output (this is not an open-drain pin). o mat3[0] ? match output for timer 3, channel 0. p0[11]/rxd2/ scl2/mat3[1] 40 [1] i/o p0[11] ? general purpose digital input/output pin. i rxd2 ? receiver input for uart2. i/o scl2 ? i 2 c2 clock input/output (this is not an open-drain pin). o mat3[1] ? match output for timer 3, channel 1. p0[15]/txd1/ sck0/sck 47 [1] i/o p0[15] ? general purpose digital input/output pin. o txd1 ? transmitter output for uart1. i/o sck0 ? serial clock for ssp0. i/o sck ? serial clock for spi. p0[16]/rxd1/ ssel0/ssel 48 [1] i/o p0[16] ? general purpose digital input/output pin. i rxd1 ? receiver input for uart1. i/o ssel0 ? slave select for ssp0. i/o ssel ? slave select for spi. p0[17]/cts1/ miso0/miso 46 [1] i/o p0[17] ? general purpose digital input/output pin. i cts1 ? clear to send input for uart1. i/o miso0 ? master in slave out for ssp0. i/o miso ? master in slave out for spi. p0[18]/dcd1/ mosi0/mosi 45 [1] i/o p0[18] ? general purpose digital input/output pin. i dcd1 ? data carrier detect input for uart1. i/o mosi0 ? master out slave in for ssp0. i/o mosi ? master out slave in for spi. table 3. pin description ?continued symbol pin type description
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 8 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller p0[22]/rts1/td1 44 [1] i/o p0[22] ? general purpose digital input/output pin. o rts1 ? request to send output for uart1. can also be configured to be an rs-485/eia-485 output enable signal. o td1 ? can1 transmitter output. p0[25]/ad0[2]/ i2srx _sda/ txd3 7 [2] i/o p0[25] ? general purpose digital input/output pin. i ad0[2] ? a/d converter 0, input 2. i/o i2srx_sda ? receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . (lpc1759/58/56 only). o txd3 ? transmitter output for uart3. p0[26]/ad0[3]/ aout/rxd3 6 [3] i/o p0[26] ? general purpose digital input/output pin. i ad0[3] ? a/d converter 0, input 3. o aout ? dac output. (lpc1759/58/56/54 only). i rxd3 ? receiver input for uart3. p0[29]/usb_d+ 22 [4] i/o p0[29] ? general purpose digital input/output pin. i/o usb_d+ ? usb bidirectional d+ line. p0[30]/usb_d ? 23 [4] i/o p0[30] ? general purpose digital input/output pin. i/o usb_d ? ? usb bidirectional d ? line. p1[0] to p1[31] i/o port 1: port 1 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block. some port pins are not available on the lqfp80 package. p1[0]/ enet_txd0 76 [1] i/o p1[0] ? general purpose digital input/output pin. o enet_txd0 ? ethernet transmit data 0. (lpc1758 only). p1[1]/ enet_txd1 75 [1] i/o p1[1] ? general purpose digital input/output pin. o enet_txd1 ? ethernet transmit data 1. (lpc1758 only). p1[4]/ enet_tx_en 74 [1] i/o p1[4] ? general purpose digital input/output pin. o enet_tx_en ? ethernet transmit data enable. (lpc1758 only). p1[8]/ enet_crs 73 [1] i/o p1[8] ? general purpose digital input/output pin. i enet_crs ? ethernet carrier sense. (lpc1758 only). p1[9]/ enet_rxd0 72 [1] i/o p1[9] ? general purpose digital input/output pin. i enet_rxd0 ? ethernet receive data. (lpc1758 only). p1[10]/ enet_rxd1 71 [1] i/o p1[10] ? general purpose digital input/output pin. i enet_rxd1 ? ethernet receive data. (lpc1758 only). p1[14]/ enet_rx_er 70 [1] i/o p1[14] ? general purpose digital input/output pin. i enet_rx_er ? ethernet receive error. (lpc1758 only). p1[15]/ enet_ref_clk 69 [1] i/o p1[15] ? general purpose digital input/output pin. i enet_ref_clk ? ethernet reference clock. (lpc1758 only). p1[18]/ usb_up_led/ pwm1[1]/ cap1[0] 25 [1] i/o p1[18] ? general purpose digital input/output pin. o usb_up_led ? usb goodlink led indicator. it is low when device is configured (non-control endpoints enabled). it is high when the device is not configured or during global suspend. o pwm1[1] ? pulse width modulator 1, channel 1 output. i cap1[0] ? capture input for timer 1, channel 0. table 3. pin description ?continued symbol pin type description
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 9 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller p1[19]/mcoa0/ usb_ppwr cap1[1] 26 [1] i/o p1[19] ? general purpose digital input/output pin. o mcoa0 ? motor control pwm channel 0, output a. o usb_ppwr ? port power enable signal for usb port. (lpc1759/58/56/54 only). i cap1[1] ? capture input for timer 1, channel 1. p1[20]/mci0/ pwm1[2]/sck0 27 [1] i/o p1[20] ? general purpose digital input/output pin. i mci0 ? motor control pwm channel 0, input. also quadrature encoder interface pha input. o pwm1[2] ? pulse width modulator 1, channel 2 output. i/o sck0 ? serial clock for ssp0. p1[22]/mcob0/ usb_pwrd/ mat1[0] 28 [1] i/o p1[22] ? general purpose digital input/output pin. o mcob0 ? motor control pwm channel 0, output b. i usb_pwrd ? power status for usb port (host power switch). (lpc1759/58/56/54 only). o mat1[0] ? match output for timer 1, channel 0. p1[23]/mci1/ pwm1[4]/miso0 29 [1] i/o p1[23] ? general purpose digital input/output pin. i mci1 ? motor control pwm channel 1, input. also quadrature encoder interface phb input. o pwm1[4] ? pulse width modulator 1, channel 4 output. i/o miso0 ? master in slave out for ssp0. p1[24]/mci2/ pwm1[5]/mosi0 30 [1] i/o p1[24] ? general purpose digital input/output pin. i mci2 ? motor control pwm channel 2, input. also quadrature encoder interface index input. o pwm1[5] ? pulse width modulator 1, channel 5 output. i/o mosi0 ? master out slave in for ssp0. p1[25]/mcoa1/ mat1[1] 31 [1] i/o p1[25] ? general purpose digital input/output pin. o mcoa1 ? motor control pwm channel 1, output a. o mat1[1] ? match output for timer 1, channel 1. p1[26]/mcob1/ pwm1[6]/cap0[0] 32 [1] i/o p1[26] ? general purpose digital input/output pin. o mcob1 ? motor control pwm channel 1, output b. o pwm1[6] ? pulse width modulator 1, channel 6 output. i cap0[0] ? capture input for timer 0, channel 0. p1[28]/mcoa2/ pcap1[0]/ mat0[0] 35 [1] i/o p1[28] ? general purpose digital input/output pin. o mcoa2 ? motor control pwm channel 2, output a. i pcap1[0] ? capture input for pwm1, channel 0. o mat0[0] ? match output for timer 0, channel 0. p1[29]/mcob2/ pcap1[1]/ mat0[1] 36 [1] i/o p1[29] ? general purpose digital input/output pin. o mcob2 ? motor control pwm channel 2, output b. i pcap1[1] ? capture input for pwm1, channel 1. o mat0[1] ? match output for timer 0, channel 1. table 3. pin description ?continued symbol pin type description
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 10 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller p1[30]/v bus / ad0[4] 18 [2] i/o p1[30] ? general purpose digital input/output pin. i v bus ? monitors the presence of usb bus power. note: this signal must be hi gh for usb reset to occur. i ad0[4] ? a/d converter 0, input 4. p1[31]/sck1/ ad0[5] 17 [2] i/o p1[31] ? general purpose digital input/output pin. i/o sck1 ? serial clock for ssp1. i ad0[5] ? a/d converter 0, input 5. p2[0] to p2[31] i/o port 2: port 2 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 2 pins depends upon the pin function selected via the pin connect block. some port pins are not available on the lqfp80 package. p2[0]/pwm1[1]/ txd1 60 [1] i/o p2[0] ? general purpose digital input/output pin. o pwm1[1] ? pulse width modulator 1, channel 1 output. o txd1 ? transmitter output for uart1. p2[1]/pwm1[2]/ rxd1 59 [1] i/o p2[1] ? general purpose digital input/output pin. o pwm1[2] ? pulse width modulator 1, channel 2 output. i rxd1 ? receiver input for uart1. p2[2]/pwm1[3]/ cts1/ tracedata[3] 58 [1] i/o p2[2] ? general purpose digital input/output pin. o pwm1[3] ? pulse width modulator 1, channel 3 output. i cts1 ? clear to send input for uart1. o tracedata[3] ? trace data, bit 3. p2[3]/pwm1[4]/ dcd1/ tracedata[2] 55 [1] i/o p2[3] ? general purpose digital input/output pin. o pwm1[4] ? pulse width modulator 1, channel 4 output. i dcd1 ? data carrier detect input for uart1. o tracedata[2] ? trace data, bit 2. p2[4]/pwm1[5]/ dsr1/ tracedata[1] 54 [1] i/o p2[4] ? general purpose digital input/output pin. o pwm1[5] ? pulse width modulator 1, channel 5 output. i dsr1 ? data set ready input for uart1. o tracedata[1] ? trace data, bit 1. p2[5]/pwm1[6]/ dtr1/ tracedata[0] 53 [1] i/o p2[5] ? general purpose digital input/output pin. o pwm1[6] ? pulse width modulator 1, channel 6 output. o dtr1 ? data terminal ready output for uart1. can also be configured to be an rs-485/eia-485 output enable signal. o tracedata[0] ? trace data, bit 0. p2[6]/pcap1[0]/ ri1/traceclk 52 [1] i/o p2[6] ? general purpose digital input/output pin. i pcap1[0] ? capture input for pwm1, channel 0. i ri1 ? ring indicator input for uart1. o traceclk ? trace clock. p2[7]/rd2/ rts1 51 [1] i/o p2[7] ? general purpose digital input/output pin. i rd2 ? can2 receiver input. (lpc1759/58/56 only). o rts1 ? request to send output for uart1. can also be configured to be an rs-485/eia-485 output enable signal. table 3. pin description ?continued symbol pin type description
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 11 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller p2[8]/td2/ txd2 50 [1] i/o p2[8] ? general purpose digital input/output pin. o td2 ? can2 transmitter output. (lpc1759/58/56 only). o txd2 ? transmitter output for uart2. p2[9]/ usb_connect/ rxd2 49 [1] i/o p2[9] ? general purpose digital input/output pin. o usb_connect ? signal used to switch an external 1.5 k ? resistor under software control. used with the softconnect usb feature. i rxd2 ? receiver input for uart2. p2[10]/eint0 /nmi 41 [5] i/o p2[10] ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. i eint0 ? external interrupt 0 input. i nmi ? non-maskable interrupt input. p4[0] to p4[31] i/o port 4: port 4 is a 32-bit i/o port with individual direction controls for each bit. the operation of port 4 pins depends upon the pin function selected via the pin connect block. some port pins are not available on the lqfp80 package. p4[28]/rx_mclk/ mat2[0]/txd3 65 [1] i/o p4[28] ? general purpose digital input/output pin. i rx_mclk ? i 2 s receive master clock. (lpc1759/58/56 only). o mat2[0] ? match output for timer 2, channel 0. o txd3 ? transmitter output for uart3. p4[29]/tx_mclk/ mat2[1]/rxd3 68 [1] i/o p4[29] ? general purpose digital input/output pin. i tx_mclk ? i 2 s transmit master clock. (lpc1759/58/56 only). o mat2[1] ? match output for timer 2, channel 1. i rxd3 ? receiver input for uart3. tdo/swo 1 [6] o tdo ? test data out for jtag interface. o swo ? serial wire trace output. tdi 2 [7] i tdi ? test data in for jtag interface. tms/swdio 3 [7] i tms ? test mode select for jtag interface. i/o swdio ? serial wire debug data input/output. trst 4 [7] i trst ? test reset for jtag interface. tck/swdclk 5 [6] i tck ? test clock for jtag interface. i swdclk ? serial wire clock. rstout 11 o rstout ? this is a 3.3 v pin. low on this pin indicates lpc1759/58/56/54/52/51 being in reset state. reset 14 [8] i external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. ttl with hysteresis, 5 v tolerant. xtal1 19 [9] [10] i input to the oscillator circuit and internal clock generator circuits. xtal2 20 [9] [10] o output from the oscillator amplifier. rtcx1 13 [9] [11] i input to the rtc oscillator circuit. rtcx2 15 [9] o output from the rtc oscillator circuit. v ss 24, 33, 43, 57, 66, 78 i ground: 0 v reference. table 3. pin description ?continued symbol pin type description
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 12 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller [1] 5 v tolerant pad providing digital i/o functions with ttl levels and hysteresis. [2] 5 v tolerant pad providing digital i/o functions (with ttl levels and hysteresis) and analog input. when configured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant. [3] 5 v tolerant pad providing digital i/o with ttl levels and hysteresis and analog output functi on. when configured as the dac output, digital section of the pad is disabled. [4] pad provides digital i/o and usb functi ons. it is designed in accordance with the usb specification, revision 2.0 (full-speed and low-speed mode only). this pad is not 5 v tolerant. [5] 5 v tolerant pad with 5 ns glitch filter providin g digital i/o functions with ttl levels and hysteresis. [6] 5 v tolerant pad with ttl levels and hysteresis. internal pull-up and pull-down resistors disabled. [7] 5 v tolerant pad with ttl levels and hysteresis and internal pull-up resistor. [8] 5 v tolerant pad with 20 ns glitch filter providi ng digital i/o function with ttl levels and hysteresis. [9] pad provides special analog functionality. [10] when the system oscillator is not used, connect xtal1 and xtal2 as follows: xtal1 can be left floating or can be grounded ( grounding is preferred to reduce susceptibility to noise). xtal2 should be left floating. [11] when the rtc is not used, connect vbat to v dd(reg)(3v3) and leave rtcx1 floating. v ssa 9i analog ground: 0 v reference. this should nominally be the same voltage as v ss , but should be isolated to minimize noise and error. v dd(3v3) 21, 42, 56, 77 i 3.3 v supply voltage: this is the power supply voltage for the i/o ports. v dd(reg)(3v3) 34, 67 i 3.3 v voltage regulator supply voltage: this is the supply voltage for the on-chip voltage regulator only. v dda 8i analog 3.3 v pad supply voltage: this should be nominally the same voltage as v dd(3v3) but should be isolated to minimize noise and error. this voltage is used to power the adc and dac. this pin should be tied to 3.3 v if the adc and dac are not used. vrefp 10 i adc positive reference voltage: this should be nominally the same voltage as v dda but should be isolated to minimize noise and error. level on this pin is used as a reference for adc and dac. this pin should be tied to 3.3 v if the adc and dac are not used. vrefn 12 i adc negative reference voltage: this should be nominally the same voltage as v ss but should be isolated to minimize noise and error. level on this pin is used as a reference for adc and dac. vbat 16 [11] i rtc pin power supply: 3.3 v on this pin supplies the power to the rtc peripheral. table 3. pin description ?continued symbol pin type description
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 13 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 7. functional description 7.1 architectural overview the arm cortex-m3 includes th ree ahb-lite buses: the system bus, the i-code bus, and the d-code bus (see figure 1 ). the i-code and d-code core buses are faster than the system bus and are used similarly to tightly coupled memory (tcm) interfaces: one bus dedicated for instruction fetch (i-code) and one bus for data access (d-code). the use of two core buses allows for simultaneous operati ons if concurrent operations target different devices. the lpc1759/58/56/54/52/51 use a multi- layer ahb matrix to connect the arm cortex-m3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 7.2 arm cortex-m3 processor the arm cortex-m3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumptio n. the arm cortex-m3 offers many new features, including a thumb-2 instruction set, low interrupt latenc y, hardware divide, interruptable/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wakeup in terrupt controller, and multiple core buses cap able of simultaneous accesses. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm cortex-m3 processor is described in detail in the cortex-m3 technical reference manual that can be found on official arm website. 7.3 on-chip flash program memory the lpc1759/58/56/54/52/51 contain up to 512 kb of on-chip flash memory. a new two-port flash accelerator maximizes perfor mance for use with the two fast ahb-lite buses. 7.4 on-chip sram the lpc1759/58/56/54/52/51 contain a total of up to 64 kb on-chip static ram memory. this includes the main 32/16/8 kb sram, acce ssible by the cpu and dma controller on a higher-speed bus, and up to two additional 16 kb each sram blocks situated on a separate slave port on the ahb multilayer matrix. this architecture allows cpu and dma accesses to be spread over three separate rams that can be accessed simultaneously. 7.5 memory protection unit (mpu) the lpc1759/58/56/54/52/51 have a memory protection unit (mpu) which can be used to improve the reliability of an embedded system by protecting critical data within the user application.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 14 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller the mpu allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses th at could potentially break the system. the mpu separates the memory into distinct regions and implements protection by preventing disallowed accesses. the mpu supports up to 8 regions each of which can be divided into 8 subregions. accesses to memory locations that are not defined in the mpu regions, or not permitted by the region setting, will cause the memory management fault exception to take place. 7.6 memory map the lpc1759/58/56/54/52/51 incorporate severa l distinct memory regions, shown in the following figures. figure 3 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb peripheral area is 2 mb in size, and is divided to allow for up to 128 peripherals. the apb peripheral area is 1 mb in size and is divided to allow for up to 64 peripherals. each peripheral of either type is allocated 16 kb of space. this allows simplifying the address decoding for each peripheral.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 15 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller fig 3. lpc1759/58/56/54/52/51 memory map 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4002 c000 0x4003 4000 0x4003 0000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 c000 0x4006 0000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 apb1 peripherals 0x4008 0000 0x4008 8000 0x4008 c000 0x4009 0000 0x4009 4000 0x4009 8000 0x4009 c000 0x400a 0000 0x400a 4000 0x400a 8000 0x400a c000 0x400b 0000 0x400b 4000 0x400b 8000 0x400b c000 0x400c 0000 0x400f c000 0x4010 0000 ssp0 dac (3) timer 2 timer 3 uart2 uart3 reserved i2s (1) i2c2 1 - 0 reserved 2 3 4 5 6 7 8 9 10 reserved repetitive interrupt timer 11 12 reserved motor control pwm 30 - 16 reserved 13 14 15 system control 31 reserved reserved 32 kb local static ram (lpc1759/8) reserved reserved private peripheral bus 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x0000 8000 0x1000 4000 16 kb local static ram (lpc1756/4/2) 0x1000 2000 8 kb local static ram (lpc1751) 0x1000 0000 0x1000 8000 0x1fff 0000 0x1fff 2000 0x2008 0000 0x2008 4000 0x2200 0000 0x200a 0000 0x2009 c000 0x2400 0000 0x4000 0000 0x4008 0000 0x4010 0000 0x4200 0000 0x4400 0000 0x5000 0000 0x5020 0000 0xe000 0000 0xe010 0000 0xffff ffff reserved reserved gpio reserved reserved reserved reserved apb0 peripherals ahb peripherals apb1 peripherals ahb sram bit-band alias addressing peripheral bit-band alias addressing 16 kb ahb sram1 (lpc1759/8) 0x2007 c000 16 kb ahb sram0 (lpc1759/8/6/4) lpc1759/58/56/54/52/51 memory space 32 kb on-chip flash (lpc1751) 0x0001 0000 64 kb on-chip flash (lpc1752) 0x0002 0000 128 kb on-chip flash (lpc1754) 0x0004 0000 256 kb on-chip flash (lpc1756) 0x0008 0000 512 kb on-chip flash (lpc1759/8) qei apb0 peripherals wdt timer 0 timer 1 uart0 uart1 reserved reserved spi rtc + backup registers gpio interrupts pin connect ssp1 adc can af ram can af registers can common can1 can2 (1) 22 - 19 reserved i2c1 31 - 24 reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 pwm1 8 kb boot rom 0x0000 0000 0x0000 0400 active interrupt vectors + 256 words i-code/d-code memory space 002aae154 (1) lpc1759/58/56 only (2) lpc1758 only (3) lpc1759/58/56/54 only 0x5000 0000 0x5000 4000 0x5000 8000 0x5000 c000 0x5020 0000 0x5001 0000 ahb peripherals ethernet controller (2) usb controller reserved 127- 4 reserved gpdma controller 0 1 2 3
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 16 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 7.7 nested vectored inte rrupt controller (nvic) the nvic is an integral part of the cortex-m 3. the tight coupling to the cpu allows for low interrupt latency and efficient processing of late arriving interrupts. 7.7.1 features ? controls system exceptions and peripheral interrupts ? in the lpc1759/58/56/54/52/51, the nvic supports 33 vectored interrupts ? 32 programmable interrupt priority levels , with hardware pr iority level masking ? relocatable vector table ? non-maskable in terrupt (nmi) ? software interr upt generation 7.7.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. any pin on port 0 and port 2 (total of 30 pi ns) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. 7.8 pin connect block the pin connect block allows selected pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activi ty of any enabled peripheral function that is not mapped to a related pin should be considered undefined. most pins can also be configured as open-drai n outputs or to have a pull-up, pull-down, or no resistor enabled. 7.9 general purpose dma controller the gpdma is an amba ahb complia nt peripheral allowing selected lpc1759/58/56/54/52/51 peripherals to have dma support. the gpdma enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. the source and destination areas can each be either a memory region or a peripheral, and can be accessed through the ahb master. the gpdma controller allows data transfers between the usb and ethernet (lpc1758 only) controlle rs and the various on-chip sram areas. the supported apb pe ripherals are ssp0/1, all uarts, the i 2 s-bus interface, the adc, and the dac. two match signals for each time r can be used to trigger dma transfers. remark: note that the dac is not available on the lpc1752/51, and the i 2 s-bus interface is not available on the lpc1754/52/51.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 17 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 7.9.1 features ? eight dma channels. each channel can support an unidirectional transfer. ? 16 dma request lines. ? single dma and burst dma request signals. each peripheral connected to the dma controller can assert either a burst dma request or a single dma request. the dma burst size is set by programming the dma controller. ? memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. ? scatter or gather dma is supported through the use of linked lists. this means that the source and destination areas do not hav e to occupy contiguous areas of memory. ? hardware dma ch annel priority. ? ahb slave dma programming interface. the dma controller is programmed by writing to the dma control regist ers over the ahb slave interface. ? one ahb bus master for transferring data. the interface transfers data when a dma request goes active. ? 32-bit ahb master bus width. ? incrementing or non-incrementing addressing for source and destination. ? programmable dma burst size. the dma burst size can be programmed to more efficiently transfer data. ? internal four-word fifo per channel. ? supports 8, 16, and 32-bit wide transactions. ? big-endian and little-endian support. the dma controller defaults to little-endian mode on reset. ? an interrupt to the processor can be generated on a dma completion or when a dma error has occurred. ? raw interrupt status. the dma error and dma count raw interrupt status can be read prior to masking. 7.10 fast general purpose parallel i/o device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically conf igured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back as well as the current state of the port pins. lpc1759/58/56/54/52/51 use accelerated gpio functions: ? gpio registers are accessed through the ahb multilayer bus so that the fastest possible i/o timing can be achieved. ? mask registers allow treating sets of por t bits as a group, leaving other bits unchanged. ? all gpio registers are byte and half-word addressable. ? entire port value can be written in one instruction. ? support for cortex-m3 bit banding. ? support for use with the gpdma controller.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 18 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller additionally, any pin on port 0 and port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. the edge detection is asynchronous, so it may operate when clocks are not present such as during power-down mode. each enabled interrupt can be used to wake up the chip from power-down mode. 7.10.1 features ? bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. ? direction control of individual bits. ? all i/o default to inputs after reset. ? pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each gpio pin. 7.11 ethernet (lpc1758 only) the ethernet block contains a full featur ed 10 mbit/s or 100 mbit/s ethernet mac designed to provide optimized performa nce through the use of dma hardware acceleration. features include a generous suite of control registers, half or full duplex operation, flow control, cont rol frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on lan activity. automatic frame transmission and reception with scatter-gather dma off-loads many operations from the cpu. the ethernet block and the cpu share the arm cortex-m3 d-code and system bus through the ahb-multilayer matrix to access the various on-chip sram blocks for ethernet data, control, and status information. the ethernet block interfaces between an off-chip ethernet phy using the reduced mii (rmii) protocol and the on-chip media independent interface management (miim) serial bus. the ethernet block supports bus clock rates of up to 100 mhz. 7.11.1 features ? ethernet standards support: ? supports 10 mbit/s or 100 mbit/s phy dev ices including 10 base-t, 100 base-tx, 100 base-fx, and 100 base-t4. ? fully compliant with ieee standard 802.3 . ? fully compliant with 802.3x full duplex fl ow control and half duplex back pressure. ? flexible transmit and receive frame options. ? virtual local area network (vlan) frame support. ? memory management: ? independent transmit and receive buffers memory mapped to shared sram. ? dma managers with scatter/gather dma and arrays of frame descriptors. ? memory traffic optimized by buffering and pre-fetching. ? enhanced ethernet features:
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 19 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller ? receive filtering. ? multicast and broadcast frame support for both transmit and receive. ? optional automatic frame check sequence (fcs) insertion with cyclic redundancy check (crc) for transmit. ? selectable automatic transmit frame padding. ? over-length frame support for both transmit and receive allows any length frames. ? promiscuous receive mode. ? automatic collision back-off and frame retr ansmission. ? includes power management by clock switching. ? wake-on-lan power management support allows system wake-up: using the receive filters or a magic frame detection filter. ? physical interface: ? attachment of external phy chip through standard rmii interface. ? phy register access is available via the miim interface. 7.12 usb interface the universal serial bu s (usb) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. the host controller allocates the usb bandwidth to attached devices through a token-based protocol. the bus supports hot plugging and dynamic configuration of the devi ces. all transactions are initiated by the host controller. the lpc1759/58/56/54 usb interface include s a device, host, and otg controller with on-chip phy for device and host functions. the otg switching protocol is supported through the use of an external controller. de tails on typical usb in terfacing solutions can be found in section 14.1 . the lpc1752/51 include a usb device controller only. 7.12.1 usb device controller the device controller enables 12 mbit/s data exchange with a usb host controller. it consists of a register interface, serial interface engine, endpoint buffer memory, and a dma controller. the serial interface engine dec odes the usb data stream and writes data to the appropriate endpoint buffer. the status of a completed usb transfer or error condition is indicated via status registers. an interrupt is also generated if enabled. when enabled, the dma controller transfers data be tween the endpoint buffer and the on-chip sram. 7.12.1.1 features ? fully compliant with usb 2.0 specification (full speed) . ? supports 32 physical (16 logical) endpoints with a 4 kb endpoint buffer ram. ? supports control, bulk, interrupt and isochronous endpoints. ? scalable realization of endpoints at run time. ? endpoint maximum packet size selection (up to usb maximum specification) by software at run time. ? supports softconnect and goodlink features.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 20 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller ? while usb is in the suspend mode, the lpc1759/58/56/54/52/51 can enter one of the reduced power modes and wake up on usb activity. ? supports dma transfers with all on-chip sram blocks on all non-control endpoints. ? allows dynamic switching between cpu-controlled slave and dma modes. ? double buffer implementation for bulk and isochronous endpoints. 7.12.2 usb host controller (lpc1759/58/56/54 only). the host controller enables fu ll- and low-speed data exchange with usb devices attached to the bus. it consists of a register interface, a serial interface engine, and a dma controller. the register interf ace complies with the open host controller interface (ohci) specification. 7.12.2.1 features ? ohci compliant. ? one downstream port. ? supports port power switching. 7.12.3 usb otg controller (lpc1759/58/56/54 only). usb otg is a supplement to the usb 2.0 specification that augmen ts the capability of existing mobile devices and usb peripherals by adding host functiona lity for connection to usb peripherals. the otg controller integrates the host contro ller, device controller, and a master-only i 2 c-bus interface to implement otg dual-rol e device functionality. the dedicated i 2 c-bus interface controls an ex ternal otg transceiver. 7.12.3.1 features ? fully compliant with on-the-go supplement to the u sb 2.0 specification, revision 1.0a . ? hardware support for host negotiation protocol (hnp). ? includes a programmable timer required for hnp and session request protocol (srp). ? supports any otg transceiver compliant with the otg transceiver specification (cea-2011), rev. 1.0 . 7.13 can controller and acceptance filters the controller area network (can) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. its domain of application ranges from high-speed ne tworks to low cost multiplex wiring. the can block is intended to support multip le can buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of can buses in industrial or automotive applications. remark: lpc1754/52/51 have only one can bus.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 21 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 7.13.1 features ? one or two can controllers and buses. ? data rates to 1 mbit/s on each bus. ? 32-bit register and ram access. ? compatible with can specification 2.0b, iso 11898-1 . ? global acceptance filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all can buses. ? acceptance filter can provide fullcan-s tyle automatic reception for selected standard identifiers. ? fullcan messages can gen erate interrupts. 7.14 12-bit adc the lpc1759/58/56/54/52/51 contain one ad c. it is a single 12-bit successive approximation adc with six channels and dma support. 7.14.1 features ? 12-bit successive approximation adc. ? input multiplexing among 6 pins. ? power-down mode. ? measurement range vrefn to vrefp. ? 12-bit conversion rate: 200 khz. ? individual channels can be selected for conversion. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of input pin or timer match signal. ? individual result registers for each adc channel to reduce interrupt overhead. ? dma support. 7.15 10-bit dac (lpc1759/58/56/54 only) the dac allows to generate a variable analog output. the maximum output value of the dac is vrefp. 7.15.1 features ? 10-bit dac ? resistor string architecture ? buffered output ? power-down mode ? selectable output drive ? dedicated conversion timer ? dma support
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 22 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 7.16 uarts the lpc1759/58/56/54/52/51 each contain four uarts. in addition to standard transmit and receive data lines, uart1 also provides a full modem control handshake interface and support for rs-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. the uarts include a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.16.1 features ? maximum uart data bit rate of 6.25 mbit/s. ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? fractional divider for baud rate control, auto baud capabilities and fifo control mechanism that enables software flow control implementation. ? uart1 equipped with standard modem interface signals. this module also provides full support for hardware flow control (auto-cts/rts). ? support for rs-485/9-bit /eia-485 mode (uart1). ? uart3 includes an irda mode to support infrared communication. ? all uarts have dma support. 7.17 spi serial i/o controller the lpc1759/58/56/54/52/51 co ntain one spi controller. spi is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 7.17.1 features ? maximum spi data bit rate of 12.5 mbit/s ? compliant with spi specification ? synchronous, serial, full duplex communication ? combined spi master and slave ? maximum data bit rate of one eighth of the input clock rate ? 8 bits to 16 bits per transfer 7.18 ssp serial i/o controller the lpc1759/58/56/54/52/51 contain two ssp controllers. the ssp controller is capable of operation on a spi, 4-wire ssi, or microwir e bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 23 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller bus during a given data transfer . the ssp supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the ma ster to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.18.1 features ? maximum ssp speed of 50 mbit/s (master) or 8 mbit/s (slave) ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame ? dma transfers supported by gpdma 7.19 i 2 c-bus serial i/o controllers the lpc1759/58/56/54/52/51 each contain two i 2 c-bus controllers. the i 2 c-bus is bidirectional for inter-ic control using only two wires: a serial clock line (scl) and a serial data line (sda). each de vice is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 7.19.1 features ? i 2 c1 and i 2 c2 use standard i/o pins with bit rates of up to 400 kbit/s (fast i 2 c-bus). ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? both i 2 c-bus controllers support multiple address recognition and a bus monitor mode. 7.20 i 2 s-bus serial i/o contro llers (lpc1759/58/56 only) the i 2 s-bus provides a standard communication interface for digital audio applications.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 24 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller the i 2 s-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. the basic i 2 s connection has one master, which is always the master, and one slave. the i 2 s-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.20.1 features ? the interface has separate input/output chan nels each of which can operate in master or slave mode. ? capable of handling 8-bit, 16-bit, and 32-bit word sizes. ? mono and stereo audio data supported. ? the sampling frequency can range from 16 khz to 96 khz (16, 22.05, 32, 44.1, 48, 96) khz. ? support for an audio master clock. ? configurable word select period in master mode (separately for i 2 s input and output). ? two 8-word fifo data buffers are provided, one for transmit and one for receive. ? generates interrupt requests when buffer levels cross a programmable boundary. ? two dma requests, controlled by programma ble buffer levels. these are connected to the gpdma block. ? controls include reset, stop and mute options separately for i 2 s input and i 2 s output. 7.21 general purpose 32-bit time rs/external event counters the lpc1759/58/56/54/52/51 include four 32 -bit timer/counters. the timer/counter is designed to count cycles of the system derive d clock or an externally-supplied clock. it can optionally generate interrupts, generate ti med dma requests, or perform other actions at specified timer values, based on four matc h registers. each time r/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.21.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation. ? two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 25 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller ? up to two match registers can be used to generate timed dma requests. 7.22 pulse width modulator the pwm is based on the standard timer block and inherits all of its features, although only the pwm function is pinned out on the lpc1759/58/56/54/52/51. the timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. the pwm function is in addi tion to these features , and is based on match register events. the ability to separately contro l rising and falling edge locations allo ws the pwm to be used for more applications. for instance, mu lti-phase motor control typically requires three non-overlapping pwm outputs with individual control of all three pulse widths and positions. two match registers can be used to provide a single edge controlled pwm output. one match register (pwmmr0) controls the pwm cycle rate, by resetting the count upon match. the other match register controls th e pwm edge position. additional single edge controlled pwm outputs require only one match re gister each, since the repetition rate is the same for all pwm outputs. multiple single edge contro lled pwm outputs will all have a rising edge at the beginning of each pwm cycle, when an pwmmr0 match occurs. three match registers can be used to provid e a pwm output with both edges controlled. again, the pwmmr0 match register contro ls the pwm cycle rate. the other match registers control the two pwm edge positi ons. additional double edge controlled pwm outputs require only two match registers each, si nce the repetition rate is the same for all pwm outputs. with double edge controlled pwm outputs, spec ific match registers control the rising and falling edge of the output. this allows both positive going pwm pulses (when the rising edge occurs prior to the falling edge), and negative goi ng pwm pulses (when the falling edge occurs prior to the rising edge). 7.22.1 features ? lpc1759/58/56/54/52/51 has one pwm block with counter or timer operation (may use the peripheral clock or one of the capture inputs as the clock source). ? seven match registers allow up to 6 single edge controlled or 3 double edge controlled pwm outputs, or a mix of bot h types. the match registers also allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? supports single edge controlled and/or double edge controlled pwm outputs. single edge controlled pwm outputs all go high at the beginning of each cycle unless the output is a constant low. double edge controlled pwm outputs can have either edge occur at any position within a cycle. this a llows for both positive going and negative going pulses. ? pulse period and width can be any number of timer counts. this allows complete flexibility in the trad e-off between resolution and re petition rate. all pwm outputs will occur at the same repetition rate.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 26 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller ? double edge controlled pwm outputs can be programmed to be either positive going or negative going pulses. ? match register updates are synchronized wit h pulse outputs to prevent generation of erroneous pulses. software must ?release? new match values before they can become effective. ? may be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler if the pwm mode is not enabled. 7.23 motor control pwm the motor control pwm is a specialized pwm supporting 3-phase motors and other combinations. feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. at the same time, the motor control pwm is highly configurable for other generalized timing, counting, capture, and compare applications. 7.24 quadrature encoder interface (qei) a quadrature encoder, also known as a 2-chan nel incremental encoder, converts angular displacement into two pulse signals. by mo nitoring both the number of pulses and the relative phase of the two signals, the user ca n track the position, direction of rotation, and velocity. in addition, a third channel, or index signal, can be used to reset the position counter. the quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over ti me and determine direction of rotation. in addition, the qei can capture the velocity of the encoder wheel. 7.24.1 features ? tracks encoder position. ? increments/decrements depending on direction. ? programmable for 2 ? or 4 ? position counting. ? velocity capture using built-in timer. ? velocity compare function with ?less than? interrupt. ? uses 32-bit registers for position and velocity. ? three position compare registers with interrupts. ? index counter for re volution counting. ? index compare register with interrupts. ? can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. ? digital filter with prog rammable delays for encoder input signals. ? can accept decoded signal inputs (clk and direction). ? connected to apb.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 27 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 7.25 repetitive inte rrupt (ri) timer the repetitive interrupt timer provides a free-r unning 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. any bits of the timer/compare can be masked such that they do not contribute to the match detection. the repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 7.25.1 features ? 32-bit counter running from pclk. counter can be free-running or be reset by a generated interrupt. ? 32-bit compare value. ? 32-bit compare mask. an interrupt is generated when the counter value equals the compare value, after masking. this allows for co mbinations not poss ible with a simple compare. 7.26 arm cortex-m3 system tick timer the arm cortex-m3 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exc eption at a 10 ms interval. in th e lpc1759/58/56/5 4/52/51, this timer can be clocked from the internal ahb clock or from a device pin. 7.27 watchdog timer the purpose of the watchdog is to reset the mi crocontroller within a reasonable amount of time if it enters an erroneous state. when enabl ed, the watchdog w ill generate a system reset if the user program fails to ?feed? (o r reload) the watchdog within a predetermined amount of time. 7.27.1 features ? internally resets chip if not period ically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 32-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 32 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be selected from the internal rc (irc) oscillator, the rtc oscillator, or the apb peripheral clock. this gives a wide range of potential timing choices of watchdog o peration under different power reduction conditions. it also provides the ability to run the wdt from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. ? includes lock/safe feature.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 28 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 7.28 rtc and backup registers the rtc is a set of counters for measuring ti me when system power is on, and optionally when it is off. the rtc on the lpc1759/58/56 /54/52/51 is designed to have extremely low power consumption, i.e. less than 1 ? a. the rtc will typically r un from the main chip power supply, conserving battery power while the rest of the device is powered up. when operating from a batter y, the rtc will continue working do wn to 2.1 v. battery power can be provided from a standard 3 v lithium button cell. an ultra-low power 32 khz oscillator will provid e a 1 hz clock to the time counting portion of the rtc, moving most of the power cons umption out of the time counting function. the rtc includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less th an 1 second per day error when o perated at a constant voltage and temperature. the rtc contains a small set of backup regi sters (20 bytes) for holding data while the main part of the lpc1759/58/5 6/54/52/51 is powered off. the rtc includes an alarm function that can wake up the lpc1759/58/56/54/52/51 from all reduced power modes with a time resolution of 1 s. 7.28.1 features ? measures the passage of time to maintain a calendar and clock. ? ultra low power design to support battery powered systems. ? provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? dedicated power supply pin can be connected to a battery or to the main 3.3 v. ? periodic interrupts can be generated from increments of any field of the time registers. ? backup registers (20 bytes) powered by vbat. ? rtc power supply is isolated from the rest of the chip. 7.29 clocking and power control 7.29.1 crystal oscillators the lpc1759/58/56/ 54/52/51 include thre e independent oscillators . these are the main oscillator, the irc oscillator, and the rtc osc illator. each oscillator can be used for more than one purpose as required in a particular application. any of the three clock sources can be chosen by software to drive the main pll and ultimately the cpu. following reset, the lpc1759/58 /56/54/52/51 will opera te from the inte rnal rc oscillator until switched by software. this allows system s to operate without any external crystal and the bootloader code to oper ate at a known frequency. see figure 4 for an overview of the lpc1759 /58/56/54/52/51 clock generation.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 29 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 7.29.1.1 internal rc oscillator the irc may be used as the clock source for th e wdt, and/or as the clock that drives the pll and subsequently the cpu. the nominal irc frequency is 4 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. upon power-up or any chip reset, the lpc1 759/58/56/54/52/51 use the irc as the clock source. software may later switch to one of the other available clock sources. 7.29.1.2 main oscillator the main oscillator can be used as the clock so urce for the cpu, with or without using the pll. the main oscillator also provides the clock source for the dedicated usb pll. the main oscillator operates at fr equencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the main pll. the clock selected as the pll inpu t is pllclkin. the arm processor clock frequency is referred to as cclk elsewhere in this document. the frequencies of pllclkin and cclk are the same value unless the pll is active and connected. the clock frequency for each peripheral can be selected individually and is referred to as pclk. refer to section 7.29.2 for additional information. 7.29.1.3 rtc oscillator the rtc oscillator can be used as the clock source for the rtc bl ock, the ma in pll, and/or the cpu. fig 4. lpc1759/58/56/54/52/51 cloc king generation block diagram main oscillator internal rc oscillator rtc oscillator main pll watchdog timer real-time clock cpu clock divider peripheral clock generator usb block arm cortex-m3 ethernet block dma gpio nvic usb clock divider system clock select (clksrcsel) usb clock config (usbclkcfg) cpu clock config (cclkcfg) pllclk cclk/8 cclk/6 cclk/4 cclk/2 cclk pclk wdt rtclk = 1hz usbclk (48 mhz) cclk usb pll usb pll enable main pll enable 32 khz apb peripherals lpc17xx 002aad947
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 30 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 7.29.2 main pll (pll0) the pll0 accepts an input clock frequency in the range of 32 khz to 25 mhz. the input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the cpu and/or the usb block. the pll0 input, in the range of 32 khz to 25 mhz, may initially be divided down by a value ?n?, which may be in the r ange of 1 to 256. this input division provides a wide range of output frequencies from the same input frequency. following the pll0 input divider is the pll0 mult iplier. this can multiply the input divider output through th e use of a current controlled oscilla tor (cco) by a value ?m?, in the range of 1 through 32768. the resulting frequency must be in the range of 275 mhz to 550 mhz. the multiplier works by dividing the cco output by the value of m, then using a phase-frequency detector to compare the divided cco output to the multiplier input. the error value is used to adjust the cco frequency. the pll0 is turned off and bypassed following a chip reset and by entering power-down mode. pll0 is enabled by software only. the program must configure and activate the pll0, wait for the pll0 to lock, and then connect to the pll0 as a clock source. 7.29.3 usb pll (pll1) the lpc1759/58/56/54/52/51 contain a second , dedicated usb pll1 to provide clocking for the usb interface. the pll1 receives its clock input from the main oscillator only and provides a fixed 48 mhz clock to the usb block only. the pll1 is disabled and powered off on reset. if the pll1 is left disabled, the usb clock will be supplied by the 48 mhz clock from the main pll0. the pll1 accepts an input clock frequency in the range of 10 mhz to 25 mhz only. the input frequency is multiplied up the range of 48 mhz for the usb clock using a current controlled oscillators (cco). it is insured that the pll1 output has a 50 % duty cycle. 7.29.4 wake-up timer the lpc1759/58/56/54/52/51 begin operation at power-up and when awakened from power-down mode by using the 4 mhz irc oscilla tor as the clock source . this allows chip operation to resume quickly. if the main oscillator or the pll is needed by the application, software will need to enable th ese features and wait for them to stabilize before they are used as a clock source. when the main oscillator is init ially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. this is im portant at power on, all types of reset, and whenever any of the aforemen tioned functions are turned off for any reason. since the oscillator and other functions are turned off during power-down mode, any wake-up of the processor from power-down mode makes use of the wake-up timer. the wake-up timer monitors the crystal oscillator to check whether it is safe to begin code execution. when power is applied to th e chip, or when some event caused the chip to exit power-down mode , some time is requir ed for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd(3v3) ramp (in the case of power on), the type of crystal and its
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 31 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 7.29.5 power control the lpc1759/58/56/54/52/51 support a variety of power control features. there are four special modes of processor power reduction: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. the cpu clock rate may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power versus processing speed based on application requirements. in addition, peripheral power control allows shutting down the clocks to individual on-chip pe ripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. each of the peripherals has its own clock divider which provides even better power control. integrated pmu (power management unit) au tomatically adjust inte rnal regulators to minimize power consumption during slee p, deep sleep, power-down, and deep power-down modes. the lpc1759/58/56/54/52/51 also implement a separate power domain to allow turning off power to the bulk of the device while main taining operation of the rtc and a small set of registers for storing data du ring any of the power-down modes. 7.29.5.1 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.29.5.2 deep-sleep mode in deep-sleep mode, the oscilla tor is shut down and the chip receives no internal clocks. the processor state and registers, peripheral registers, and internal sram values are preserved throughout deep-sleep mode and the logic levels of chip pins remain static. the output of the irc is disabled but the irc is not powered down for a fast wake-up later. the rtc oscillator is not stopped because the rtc interrupts may be used as the wake-up source. the pll is automatically turned off and disconnected. the cclk and usb clock dividers automati cally get reset to zero. the deep-sleep mode can be terminated a nd normal operation resumed by either a reset or certain specific inte rrupts that are able to function without clocks. since all dynamic operation of the chip is suspended, deep-sleep mode reduces chip power consumption to a very low value. power to th e flash memory is left on in deep-sleep mode, allowing a very quick wake-up.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 32 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller on wake-up from deep-sleep mode, the code execution an d peripherals activities will resume after 4 cycles expire if the irc was used before entering deep-sleep mode. if the main external oscillator wa s used, the code execution w ill resume when 4096 cycles expire. pll and clock dividers need to be reconfigured accordingly. 7.29.5.3 power-down mode power-down mode does everythi ng that deep-sleep mode does, but also turns off the power to the irc oscillator an d the flash memory. this save s more power but requires waiting for resumption of flash operation befo re execution of code or data access in the flash memory can be accomplished. on the wake-up of power-down mode, if the irc was used before entering power-down mode, it will take irc 60 ? s to start-up. after this 4 irc cycles will expire before the code execution can then be resumed if the code was running from sram. in the meantime, the flash wake-up timer then counts 4 mhz irc clock cycles to make the 100 ? s flash start-up time. when it times out, access to the flash will be allowed. users need to reconfigure the pll and clock dividers accordingly. 7.29.5.4 deep power-down mode the deep power-down mode can only be entered from the rtc block. in deep power-down mode, power is shut off to the entire chip with the exception of the rtc module and the reset pin. the lpc1759/58 /56/54/52/51 can wa ke up from deep power- down mode via the reset pin or an alarm match event of the rtc. 7.29.5.5 wakeup interrupt controller the wakeup interrupt controller (wic) allows the cpu to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in deep sleep, power-down, and deep power-down modes. the wakeup interrupt controller (wic) works in connection with the nested vectored interrupt controller (n vic). when the cpu enters deep sleep, power-down, or deep power-down mode, the nvic sends a mask of the current interrupt situation to the wic.this mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. with this informat ion, the wic simply notices when one of the interrupts has occurred and then it wakes up the cpu. the wakeup interrupt controller (wic) eliminates the need to periodically wake up the cpu and poll the interrupts result ing in additional power savings. 7.29.6 peripheral power control a power control for peripherals feature allows i ndividual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. 7.29.7 power domains the lpc1759/58/56/54/52/51 prov ide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the rtc and the backup registers.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 33 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller on the lpc1759/58/56/54/52/51, i/o pads are powered by the 3.3 v (v dd(3v3) ) pins, while the v dd(reg)(3v3) pin powers the on-chip voltage regulator which in turn provides power to the cpu and most of the peripherals. depending on the lpc1759/58/56/54/52/51 application, a design can use two power options to manage power consumption. the first option assumes that power consumptio n is not a concern and the design ties the v dd(3v3) and v dd(reg)(3v3) pins together. this approach requires only one 3.3 v power supply for both pads, the cpu, and peripherals. while this solution is simple, it does not support powering down the i/o pad ring ?on the fly? while keeping the cpu and peripherals alive. the second option uses two power supplie s; a 3.3 v supply for the i/o pads (v dd(3v3) ) and a dedicated 3.3 v supply for the cpu (v dd(reg)(3v3) ). having the on-chip voltage regulator powered independently from the i/o pad ring enables shutting down of the i/o pad power supply ?on the fly?, while the cpu and peripherals stay active. the vbat pin supplies power only to the rtc domain. the rtc requires a minimum of power to operate, which can be supplied by an external battery. the device core power (v dd(reg)(3v3) ) is used to operate the rtc whenever v dd(reg)(3v3) is present. therefore, there is no power drain from the rtc battery when v dd(reg)(3v3) is available.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 34 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 7.30 system control 7.30.1 reset reset has four sources on the lpc17xx: the reset pin, the watchdog reset, power-on reset (por), and the brownout detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, causes the rstout pin to go low and starts the wake-up timer (see description in section 7.29.4 ). the wake-up timer ensures that reset remains asserted until the external reset is de-a sserted, the oscillator is runnin g, a fixed number of clocks have passed, and the flash controller has co mpleted its initialization. once reset is de-asserted, or, in case of a bod-triggered reset, once the voltage rises above the bod threshold, the rstout pin goes high. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. fig 5. power distribution real-time clock backup registers regulator 32 khz oscillator rtc power domain main power domain 002aad978 rtcx1 vbat v dd(reg)(3v3) rtcx2 v dd(3v3) v ss to memories, peripherals, oscillators, plls to core to i/o pads adc dac adc power domain v dda vrefp vrefn v ssa lpc17xx ultra low-power regulator power selector
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 35 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 7.30.2 brownout detection the lpc1759/58/56/54/52/51 include 2-st age monitoring of the voltage on the v dd(reg)(3v3) pins. if this voltage falls below 2.2 v, the bod asserts an interrupt signal to the vectored interrupt controller. this signal can be enabled for interrupt in the interrupt enable register in the nvic in order to cause a cpu interrupt; if not, software can monitor the signal by reading a dedicated status register. the second stage of low-voltage detection asserts reset to inactivate the lpc1759/58/56/54/52/51 when the voltage on the v dd(reg)(3v3) pins falls below 1.85 v. this reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. the bod circ uit maintains this reset down below 1 v, at which point the power-on reset circuitry maintains the overall reset. both the 2.2 v and 1.85 v thresholds include some hysteresis. in normal operation, this hysteresis allows the 2.2 v detection to relia bly interrupt, or a regularly executed event loop to sense the condition. 7.30.3 code security (code read protection - crp) 1 this feature of the lpc1759/58/56/54/52/51 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the jtag and isp can be restricted. when needed, crp is invoked by programming a specific pattern into a dedicated flash location. iap commands are not affected by the crp. there are three levels of the code read protection. crp1 disables access to chip via the jtag and allows partial flash update (excluding flash sector 0) using a limited set of the is p commands. this mode is useful when crp is required and flash field updates are needed but all sectors can not be erased. crp2 disables access to chip via the jtag and only allows full flash erase and update using a reduced set of the isp commands. running an application with level crp3 selected fully disa bles any access to chip via the jtag pins and the isp. this mode effectively disables isp override using p2[10] pin, too. it is up to the user?s application to provide (if needed) flash update mechanism using iap calls or call reinvoke isp command to enable flash update via uart0. 7.30.4 apb interface the apb peripherals are split into two separa te apb buses in order to distribute the bus bandwidth and thereby reducing stalls caus ed by contention between the cpu and the gpdma controller. 1. LPC1751FBD80 with device id 25001110 does not support crp feature. LPC1751FBD80 with device id 25001118 does support crp. see errata note in es_lpc1751. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 36 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 7.30.5 ahb multilayer matrix the lpc1759/58/56/54/52/51 use an ahb mult ilayer matrix. this ma trix connects the instruction (i-code) and data (d-code) cpu buses of the arm cortex-m3 to the flash memory, the main (32 kb) static ram, and the boot rom. the gpdma can also access all of these memories. the peripheral dma controllers, ethernet (lpc1758 only) and usb, can access all sram blocks. additionally , the matrix connects the cpu system bus and all of the dma controllers to the various peripheral functions. 7.30.6 external interrupt inputs the lpc1759/58/56/54/52/51 include up to 30 edge sensitive interrupt inputs combined with one level sensitive external interrupt input as selectable pin function. the external interrupt input can optionally be used to wake up the processor from power-down mode. 7.30.7 memory mapping control the cortex-m3 incorporates a me chanism that allows remapping the interrupt vector table to alternate locations in the memory map. th is is controlled via the vector table offset register contained in the nvic. the vector table may be located anywhere within the bottom 1 gb of cortex-m3 address space. the vector table must be located on a 128 word (512 byte) boundary because the nvic on the lpc1759/58/56 /54/52/51 is configured for 128 total interrupts. 7.31 emulation and debugging debug and trace functions are integrated in to the arm cortex-m3. serial wire debug and trace functions are supported in addition to a standard jtag debug and parallel trace functions. the arm cortex-m3 is configured to support up to eight breakpoints and four watch points.
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 37 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] not to exceed 4.6 v. [4] the peak current is limited to 25 times the corresponding maximum current. [5] dependent on package type. [6] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 4. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) external rail 2.4 3.6 v v dd(reg)(3v3) regulator supply voltage (3.3 v) 2.4 3.6 v v dda analog 3.3 v pad supply voltage ? 0.5 +4.6 v v i(vbat) input voltage on pin vbat for the rtc ? 0.5 +4.6 v v i(vrefp) input voltage on pin vrefp ? 0.5 +4.6 v v ia analog input voltage on adc related pins ? 0.5 +5.1 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd(3v3) supply voltage is present [2] ? 0.5 +5.5 v other i/o pins [2] [3] ? 0.5 v dd(3v3) + 0.5 v i dd supply current per supply pin [4] - 100 ma i ss ground current per ground pin [4] - 100 ma i latch i/o latch-up current ? (0.5v dd(3v3) ) < v i < (1.5v dd(3v3) ); t j < 125 ? c - 100 ma t stg storage temperature [5] ? 65 +150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [6] ? 4000 +4000 v
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 38 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 9. thermal characteristics 9.1 thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. t j t amb p d r th j a ? ?? ? ?? += table 5. thermal characteristics v dd = 2.4 v to 3.6 v; t amb = ? ? ? symbol parameter conditions min typ max unit t j(max) maximum junction temperature --125 ? c
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 39 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 10. static characteristics table 6. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit supply pins v dd(3v3) supply voltage (3.3 v) external rail [2] 2.4 3.3 3.6 v v dd(reg)(3v3) regulator supply voltage (3.3 v) 2.4 3.3 3.6 v v dda analog 3.3 v pad supply voltage 2.7 3.3 3.6 v v i(vbat) input voltage on pin vbat [3] 2.1 3.3 3.6 v v i(vrefp) input voltage on pin vrefp 2.7 3.3 v dda v i dd(reg)(3v3) regulator supply current (3.3 v) active mode; code while(1){} executed from flash; all peripherals disabled; pclk = cclk ? 8 cclk = 12 mhz; pll disabled [4] [5] -7-m a cclk = 100 mhz; pll enabled [4] [5] -4 2-m a cclk = 100 mhz; pll enabled (lpc1759) [4] [6] 50 cclk = 120 mhz; pll enabled (lpc1759) [4] [6] -6 7-m a sleep mode [4] [7] -2-m a deep sleep mode [4] [8] -2 4 0- ? a power-down mode [4] [8] -3 1- ? a deep power-down mode; rtc running [9] -6 3 0-n a i bat battery supply current deep power-down mode; rtc running v dd(reg)(3v3) present [10] -5 3 0-n a v dd(reg)(3v3) not present [11] - 1.1 - ? a i dd(io) i/o supply current deep sleep mode [12] -4 0-n a power-down mode [12] -4 0-n a deep power-down mode [12] -1 0-n a
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 40 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller i dd(adc) adc supply current active mode; adc powered [13] [14] -1 . 9 5-m a adc in power-down mode [13] [15] -< 0 . 2- ? a deep sleep mode [13] -3 8-n a power-down mode [13] -3 8-n a deep power-down mode [13] -2 4-n a i i(adc) adc input current on pin vrefp deep sleep mode [16] -1 0 0-n a power-down mode [16] -1 0 0-n a deep power-down mode [16] -1 0 0-n a standard port pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled - 0.5 10 na i ih high-level input current v i =v dd(3v3) ; on-chip pull-down resistor disabled - 0.5 10 na i oz off-state output current v o =0v; v o =v dd(3v3) ; on-chip pull-up/down resistors disabled - 0.5 10 na v i input voltage pin configured to provide a digital function [17] [18] [19] 0- 5 . 0v v o output voltage output active 0 - v dd(3v3) v v ih high-level input voltage 0.7v dd(3v3) --v v il low-level input voltage - - 0.3v dd(3v3) v v hys hysteresis voltage 0.4 - - v v oh high-level output voltage i oh = ? 4 ma v dd(3v3) ? 0.4 --v v ol low-level output voltage i ol = 4 m a --0 . 4v i oh high-level output current v oh =v dd(3v3) ? 0.4 v ? 4--ma i ol low-level output current v ol = 0 . 4 v 4--m a i ohs high-level short-circuit output current v oh =0v [20] --? 45 ma i ols low-level short-circuit output current v ol =v dd(3v3) [20] --5 0m a i pd pull-down current v i =5v 10 50 150 ? a i pu pull-up current v i =0v ? 15 ? 50 ? 85 ? a v dd(3v3) lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 41 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] for usb operation 3.0 v ? v dd((3v3) ? 3.6 v. guaranteed by design. [3] the rtc typically fails when v i(vbat) drops below 1.6 v. [4] v dd(reg)(3v3) = 3.3 v; t amb =25 ? c for all power consumption measurements. [5] applies to lpc1758, lpc1756, lpc1754, lpc1752, lpc1751. [6] applies to lpc1759 only. [7] irc running at 4 mhz; main o scillator and pll disabled; pclk = cclk ? 8 . [8] bod disabled. [9] on pin v dd(reg)(3v3) . i bat = 530 na. v dd(reg)(3v3) = 3.0 v; v bat = 3.0 v; t amb =25 ? c. [10] on pin vbat. i dd(reg)(3v3) = 630 na. v dd(reg)(3v3) = 3.0 v; v bat = 3.0 v. t amb =25 ? c. [11] on pin vbat. v bat = 3.0 v. t amb =25 ? c. [12] all internal pull-ups disabled. all pi ns configured as output and driven low. v dd(3v3) = 3.3 v; t amb =25 ? c. [13] v dda = 3.3 v; t amb =25 ? c. [14] the adc is powered if the pdn bit in the ad0cr register is set to 1. see lpc17xx user manual um10360 . oscillator pins v i(xtal1) input voltage on pin xtal1 ? 0.5 1.8 1.95 v v o(xtal2) output voltage on pin xtal2 ? 0.5 1.8 1.95 v v i(rtcx1) input voltage on pin rtcx1 ? 0.5 - 3.6 v v o(rtcx2) output voltage on pin rtcx2 ? 0.5 - 3.6 v usb pins i oz off-state output current 0v lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 42 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller [15] the adc is in power-down mode if the pdn bit in the ad0cr register is set to 0. see lpc17xx user manual um10360 . [16] v i(vrefp) = 3.3 v; t amb =25 ? c. [17] including voltage on outputs in 3-state mode. [18] v dd(3v3) supply voltages must be present. [19] 3-state outputs go into 3-state mode in deep power-down mode. [20] allowed as long as the current limit does not exceed the maximum current allowed by the device. [21] includes external resistors of 33 ?? 1 % on d+ and d ? . 10.1 power consumption conditions: v dd(reg)(3v3) = 3.3 v; bod disabled. fig 6. deep-sleep mode: typical regulator supply current i dd(reg)(3v3) versus temperature 002aaf568 temperature ( c) ?40 85 35 10 60 ?15 250 350 300 400 i dd(reg)(3v3) (a) 200 3.6 v 3.3 v 2.4 v
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 43 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller conditions: v dd(reg)(3v3) = 3.3 v; bod disabled. fig 7. power-down mode: typica l regulator supply current i dd(reg)(3v3) versus temperature conditions: v dd(reg)(3v3) floating; rtc running. fig 8. deep power-down mode: typical battery supply current i bat versus temperature 002aaf569 40 80 120 0 temperature ( c) ?40 85 35 10 60 ?15 i dd(reg)(3v3) (a) 3.6 v 3.3 v 2.4 v 002aag119 1.0 1.4 1.8 0.6 temperature (c) -40 85 35 10 60 -15 i bat) (a) v i(vbat) = 3.6 v 3.3 v 3.0 v 2.4 v
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 44 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller conditions: v bat = 3.0 v; v dd(reg)(3v3) = 3.0 v; rtc running. fig 9. deep power-down mode: typical regulator supply current i dd(reg)(3v3) and battery supply current i bat versus temperature 002aag120 temperature (c) -40 85 35 10 60 -15 0.8 1.6 0.4 1.2 2.0 0 i dd(reg)(3v3) i bat i dd(reg)(3v3) /i bat (a)
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 45 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 10.2 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the pconp register. all other blocks are disabled and no code is ex ecuted. measured on a typical sample at t amb =25 ? c. the peripheral clock pclk = cclk/4. [1] the combined current of several peripherals running at the sa me time can be less than the sum of each individual peripheral current measured separately. table 7. power consumption for individual analog and digital blocks peripheral conditions typical supply current in ma; cclk = notes 12 mhz 48 mhz 100 mhz timer 0.03 0.11 0.23 average current per timer uart 0.07 0.26 0.53 average current per uart pwm 0.05 0.20 0.41 motor control pwm 0.05 0.21 0.42 i2c 0.02 0.08 0.16 average current per i2c spi 0.02 0.06 0.13 ssp1 0.04 0.16 0.32 adc pclk = 12 mhz for cclk = 12 mhz and 48 mhz; pclk = 12.5 mhz for cclk = 100 mhz 2.12 2.09 2.07 can pclk = cclk/6 0.13 0.49 1.00 average current per can can0, can1, acceptance filter pclk = cclk/6 0.22 0.85 1.73 both can blocks and acceptance filter [1] dma pclk = cclk 1.33 5.10 10.36 qei 0.05 0.20 0.41 gpio 0.33 1.27 2.58 i2s 0.09 0.34 0.70 usb and pll1 0.94 1.32 1.94 ethernet ethernet block enabled in the pconp register; ethernet not connected. 0.49 1.87 3.79 ethernet connected ethernet initialized, connected to network, and running web server example. - - 5.19
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 46 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 10.3 electrical pi n characteristics conditions: v dd(reg)(3v3) = v dd(3v3) = 3.3 v; standard port pins. fig 10. typical high-level output voltage v oh versus high-level output source current i oh conditions: v dd(reg)(3v3) = v dd(3v3) = 3.3 v; standard port pins. fig 11. typical low-level output current i ol versus low-level output voltage v ol i oh (ma) 0 24 16 8 002aaf112 2.8 2.4 3.2 3.6 v oh (v) 2.0 t = 85 c 25 c ?40 c v ol (v) 0 0.6 0.4 0.2 002aaf111 5 10 15 i ol (ma) 0 t = 85 c 25 c ?40 c
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 47 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller conditions: v dd(reg)(3v3) = v dd(3v3) = 3.3 v; standard port pins. fig 12. typical pull-up current i pu versus input voltage v i conditions: v dd(reg)(3v3) = v dd(3v3) = 3.3 v; standard port pins. fig 13. typical pull-down current i pd versus input voltage v i 0 5 4 23 1 002aaf108 ?30 ?50 ?10 10 i pu (a) ?70 t = 85 c 25 c ?40 c v i (v) 002aaf109 v i (v) 0 5 3 24 1 10 70 50 30 90 i pd (a) ?10 t = 85 c 25 c ?40 c
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 48 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 11. dynamic characteristics 11.1 flash memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes from ram to t he flash. data must be written to the flash in blocks of 256 bytes. 11.2 external clock [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 8. flash characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 - - years unpowered 20 - - years t er erase time sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms table 9. dynamic character istic: external clock t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4 - - ns t clcx clock low time t cy(clk) ? 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns fig 14. external clock timing (wit h an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 49 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 11.3 internal oscillators [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. 11.4 i/o pins [1] applies to standard port pins and reset pin. table 10. dynamic characteristic: internal oscillators t amb = ? 40 ? c to +85 ? c; 2.7 v ? v dd(3v3) ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 3.96 4.02 4.04 mhz f i(rtc) rtc input frequency - - 32.768 - khz conditions: frequency values are typical values. 4 mhz ? 1 % accuracy is guaranteed for 2.7 v ? v dd(3v3) ?? 3.6 v and t amb = ?40 ? c to +85 ? c. variations between parts may cause the irc to fall outside the 4 mhz ? 1 % accuracy specification for voltages below 2.7 v. fig 15. internal rc oscillator frequency versus temperature 002aaf107 temperature ( c) ?40 85 35 10 60 ?15 4.024 4.032 4.020 4.028 4.036 f osc(rc) (mhz) 4.016 vdd(3v) = 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v table 11. dynamic characteristic: i/o pins [1] t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 50 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 11.5 i 2 c-bus [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the falling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see the i 2 c-bus specification um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with respect to the rising edge of scl; applies to data in transmission and the acknowledge. table 12. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ? c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s t su;dat data set-up time [9] standard-mode 250 - ns fast-mode 100 - ns
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 51 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller fig 16. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 52 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 11.6 i 2 s-bus interface (lpc1759/58/56 only) [1] cclk = 20 mhz; peripheral clock to the i 2 s-bus interface pclk = cclk ? 4 ; t cy(clk) = 1600 ns, corresponds to the sck signal in the i 2 s-bus specification . table 13. dynamic characteristics: i 2 s-bus interface pins t amb = ? 40 ? c to +85 ? c. symbol parameter conditions min typ max unit common to input and output t r rise time [1] - - 35 ns t f fall time [1] - - 35 ns t wh pulse width high on pins i2stx_clk and i2srx_clk [1] 0.495 ?? t cy(clk) -- - t wl pulse width low on pins i2stx_clk and i2srx_clk [1] - - 0.505 ?? t cy(clk) ns output t v(q) data output valid time on pin i2stx_sda; [1] - - 30 ns on pin i2stx_ws [1] - - 30 ns input t su(d) data input set-up time on pin i2srx_sda [1] 3.5 - - ns t h(d) data input hold time on pin i2srx_sda [1] 4.0 - - ns fig 17. i 2 s-bus timing (output) 002aad992 i2stx_clk i2stx_sda i2stx_ws t cy(clk) t f t r t wh t wl t v(q) t v(q)
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 53 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller fig 18. i 2 s-bus timing (input) 002aae159 t cy(clk) t f t r t wh t su(d) t h(d) t su(d) t su(d) t wl i2srx_clk i2srx_sda i2srx_ws
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 54 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 11.7 ssp interface [1] the peripheral clock for ssp is pclk = cclk = 20 mhz. table 14. dynamic characteristi c: ssp interface t amb =25 ? c; v dd(3v3) over specified ranges. symbol parameter conditions min typ max unit t su(spi_miso) spi_miso set-up time measur ed in spi master mode; see figure 19 [1] 30 - - ns fig 19. ssp miso line set-up time in spi master mode t su(spi_miso) sck shifting edges mosi miso 002aad326 sampling edges
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 55 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 11.8 usb interface [1] characterized but not implemented as production test. guaranteed by design. table 15. dynamic characteris tics: usb pins (full-speed) c l = 50 pf; r pu = 1.5 k ? on d+ to v dd(3v3) ; 3.0 v ? v dd(3v3) ? 3.6 v. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % 8.5 - 13.8 ns t f fall time 10 % to 90 % 7.7 - 13.7 ns t frfm differential rise and fall time matching t r /t f --1 0 9% v crs output signal crossover voltage 1.3 - 2.0 v t feopt source se0 interval of eop see figure 20 160 - 175 ns t fdeop source jitter for differential transition to se0 transition see figure 20 ? 2-+5ns t jr1 receiver jitter to next transition ? 18.5 - +18.5 ns t jr2 receiver jitter for paired transitions 10 % to 90 % ? 9-+9ns t eopr1 eop width at receiver must reject as eop; see figure 20 [1] 40 --ns t eopr2 eop width at receiver must accept as eop; see figure 20 [1] 82 --ns fig 20. differential da ta-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 56 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 11.9 spi [1] t spicyc = (t cy(pclk) ? n) ? 0.5 %, n is the spi clock divider value (n ? 8); pclk is derived from the processor clock cclk. [2] timing parameters are measured with respect to the 50 % edge of the clock pclk and the 10 % (90 %) edge of the data signal (mosi or miso). table 16. dynamic characteristics of spi pins t amb = ? 40 ? c to +85 ? c. symbol parameter min typ max unit t cy(pclk) pclk cycle time 10 - - ns t spicyc spi cycle time [1] 79.6 - - ns t spiclkh spiclk high time 0.485 ? t spicyc -- ns t spiclkl spiclk low time - 0.515 ? t spicyc ns spi master t spidsu spi data set-up time [2] 0- -n s t spidh spi data hold time [2] 2 ?? t cy(pclk) ? 5 - - ns t spiqv spi data output valid time [2] 2 ?? t cy(pclk) + 30 - - ns t spioh spi output data hold time [2] 2 ?? t cy(pclk) + 5 - - ns spi slave t spidsu spi data set-up time [2] 0- -n s t spidh spi data hold time [2] 2 ?? t cy(pclk) + 5 - - ns t spiqv spi data output valid time [2] 2 ?? t cy(pclk) + 35 - - ns t spioh spi output data hold time [2] 2 ?? t cy(pclk) + 15 - - ns fig 21. spi master timing (cpha = 1) sck (cpol = 0) mosi miso 002aad986 t spicyc t spiclkh t spiclkl t spidsu t spidh t spiqv data valid data valid t spioh sck (cpol = 1) data valid data valid
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 57 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller fig 22. spi master timing (cpha = 0) fig 23. spi slave timing (cpha = 1) sck (cpol = 0) mosi miso 002aad987 t spicyc t spiclkh t spiclkl t spidsu t spidh data valid data valid t spioh sck (cpol = 1) data valid data valid t spiqv sck (cpol = 0) mosi miso 002aad988 t spicyc t spiclkh t spiclkl t spidsu t spidh t spiqv data valid data valid t spioh sck (cpol = 1) data valid data valid
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 58 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 12. adc electrical characteristics [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 25 . [3] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 25 . [4] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 25 . [5] adcoffs value (bits 7:4) = 2 in the adtrm register. see lpc17xx user manual um10360 . [6] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 25 . [7] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 25 . [8] see figure 26 . [9] the conversion frequency corresponds to the number of samples per second. fig 24. spi slave timing (cpha = 0) sck (cpol = 0) mosi miso 002aad989 t spicyc t spiclkh t spiclkl t spidsu t spidh t spiqv data valid data valid t spioh sck (cpol = 1) data valid data valid table 17. adc characteristics (full resolution) v dda = 2.7 v to 3.6 v; t amb = ? 40 ? c to +85 ? c unless otherwise specified; adc fr equency 13 mhz; 12-bit resolution. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v c ia analog input capacitance - - 15 pf e d differential linearity error [1] [2] --? 1lsb e l(adj) integral non-linearity [3] --? 3lsb e o offset error [4] [5] --? 2lsb e g gain error [6] --0 . 5% e t absolute error [7] --4l s b r vsi voltage source interface resistance [8] --7 . 5k ? f clk(adc) adc clock frequency - - 13 mhz f c(adc) adc conversion frequency [9] --2 0 0k h z
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 59 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 25 . [3] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 25 . [4] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 25 . [5] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 25 . [6] the conversion frequency corresponds to the number of samples per second. table 18. adc characteristics (lower resolution) t amb = ? 40 ? c to +85 ? c unless otherwise specified; 12-bit a dc used as 10-bit resolution adc. symbol parameter conditions min typ max unit e d differential linearity error [1] [2] - ? 1 ? lsb e l(adj) integral non-linearity [3] - ? 1.5 - lsb e o offset error [4] - ? 2- lsb e g gain error [5] - ? 2- lsb f clk(adc) adc clock frequency 3.0 v ? v dda ? 3.6 v - - 33 mhz 2.7 v ? v dda < 3.0 v - - 25 mhz f c(adc) adc conversion frequency 3 v ? v dda ? 3.6 v [6] -- 500 khz 2.7 v ? v dda < 3.0 v [6] -- 400 khz
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 60 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 25. 12-bit adc characteristics 002aad948 4095 4094 4093 4092 4091 (2) (1) 4096 4090 4091 4092 4093 4094 4095 7 123456 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 lsb (ideal) code out vrefp ? vrefn 4096 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 61 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 13. dac electrical characteristi cs (lpc1759/58/56/54 only) the values of resistor components r i1 and r i2 vary with temperature and input voltage and are process-dependent (see table 19 ). parasitic resistance and capacitance from the pad are not included in this figure. fig 26. adc interface to pins ad0[n] table 19. adc interface components component range description r i1 2 k ? to 5.2 k ? switch-on resistance for channel selection switch. varies with temperature, input voltage, and process. r i2 100 ? to 600 ? switch-on resistance for the co mparator input switch. varies with temperature, input voltage, and process. c1 750 ff parasitic capacitance from the adc block level. c2 65 ff parasitic capacitance from the adc block level. c3 2.2 pf sampling capacitor. lpc17xx ad0[n] 750 ff 65 ff c ia 2.2 pf r vsi r i2 100 - 600 r i1 2 k - 5.2 k v ss v ext 002aaf197 adc comparator block c1 c3 c2 table 20. dac electrical characteristics v dda = 2.7 v to 3.6 v; t amb = ? 40 ? c to +85 ? c unless otherwise specified symbol parameter conditions min typ max unit e d differential linearity error - ? 1- lsb e l(adj) integral non-linearity - ? 1.5 - lsb e o offset error - 0.6 - % e g gain error - 0.6 - % c l load capacitance - 200 - pf r l load resistance 1 - - k ?
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 62 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 14. application information 14.1 suggested usb interface solutions fig 27. lpc1759/58/56/54/52/51 usb interface on a self-powered device lpc17xx usb-b connector usb_d+ usb_connect softconnect switch usb_d? v bus v ss v dd(3v3) r1 1.5 k r s = 33 002aad939 r s = 33 usb_up_led fig 28. lpc1759/58/56/54/52/51 usb interface on a bus-powered device lpc17xx v dd(3v3) r1 1.5 k r2 usb_up_led 002aad940 usb-b connector usb_d+ usb_d? v bus v ss r s = 33 r s = 33
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 63 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller fig 29. lpc1759/58/56/54 usb otg port configuration usb_d+ usb_d? sda1/2 scl1/2 rstout lpc1759/58/ 56/54 mini-ab connector 33 33 v dd v dd 002aae155 eint0 reset_n adr/psw speed suspend oe_n/int_n scl sda int_n v bus id dp dm isp1302 v ss usb_up_led v dd fig 30. lpc1759/58/56/54 usb host port configuration usb_up_led usb_d+ usb_d? usb_pwrd 15 k 15 k lpc1759/58/ 56/54 usb-a connector 33 33 002aae156 v dd usb_ppwr lm3526-l ena in 5 v flaga outa v dd d+ d? v bus v ss
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 64 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 14.2 crystal oscillator xtal input and component selection the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf ( figure 32 ), with an amplitude between 200 mv(rms) and 1000 mv(rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. external components and models used in oscillation mode are shown in figure 33 and in ta b l e 2 1 and ta b l e 2 2 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequenc y is represen ted by l, c l and r s ). capacitance c p in figure 33 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer. fig 31. lpc1759/58/56/54/52/51 usb device port configuration lpc17xx usb-b connector 33 33 002aad943 usb_up_led usb_connect v dd v dd d+ d? usb_d+ usb_d? v bus v bus v ss fig 32. slave mode operation of the on-chip oscillator lpc1xxx xtal1 c i 100 pf c g 002aae835
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 65 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 14.3 xtal printed-circuit boar d (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in fig 33. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 21. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters): low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 /c x2 1 mhz - 5 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf 5 mhz - 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz - 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz - 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 22. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters): high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , cx2 15 mhz - 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz - 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf 002aaf424 lpc1xxx xtalin xtalout c x2 c x1 xtal = c l c p r s l
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 66 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. 14.4 standard i/o pi n configuration figure 34 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver: open-drain mode enabled/disabled ? digital input: pull-up enabled/disabled ? digital input: pull-down enabled/disabled ? digital input: repeater mode enabled/disabled ? analog input the default configuration for standard i/o pi ns is input with pull-up enabled. the weak mos devices provide a drive capability equiva lent to pull-up and pull-down resistors. fig 34. standard i/o pin configuration with analog input pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable data output data input analog input select analog input 002aaf272 pin configured as digital output driver pin configured as digital input pin configured as analog input
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 67 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 14.5 reset pin configuration fig 35. reset pin configuration v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 68 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 15. package outline fig 36. package outline (lqfp80) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o o 0.15 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 sot315-1 136e15 ms-026 00-01-19 03-02-25 d (1) (1)(1) 12.1 11.9 h d 14.15 13.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 20 c d h b p e h a 2 v m b d z d a z e e v m a x 1 80 61 60 41 40 21 y pin 1 index w m w m 0 5 10 mm scale lqfp80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm sot315-1
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 69 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 16. abbreviations table 23. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brownout detection can controller area network dac digital-to-analog converter dma direct memory access eop end of packet gpio general purpose input/output irc internal rc irda infrared data association jtag joint test action group mac media access control miim media independent interface management otg on-the-go phy physical layer pll phase-locked loop pwm pulse width modulator rmii reduced media independent interface se0 single ended zero spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port ttl transistor-transistor logic uart universal asynchronous receiver/transmitter usb universal serial bus
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 70 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 17. revision history table 24. revision history document id release date data sheet status change notice supersedes lpc1759_58_56_54_52_51 v.7 20110329 product data sheet - lpc1759_58_56_54_52_51 v.6 modifications: ? pin description of pins p0[29] and p0[30] updated in table note 4 of ta b l e 3 . pins are not 5 v tolerant. ? typical value for parameter n endu added in ta b l e 8 . ? condition 3.0 v ? v dd(3v3) ? 3.6 v added in ta b l e 1 5 . ? typical values for parameters i dd(reg)(3v3) and i bat with condition deep power-down mode corrected in ta b l e 6 and table note 9 , table note 10 , and table note 11 updated. ? for deep power-down mode, figure 8 updated and figure 9 added. lpc1759_58_56_54_52_51 v.6 20100825 product data sheet - lpc1759_58_56_54_52_51 v.5 modifications: ? section 7.30.2; bod level corrected. ? added section 10.2. lpc1759_58_56_54_52_51 v.5 20100716 product data sheet - lpc1759_58_56_54_52_51 v.4 lpc1759_58_56_54_52_51 v.4 20100126 product data sheet - lpc1758_56_54_52_51 v.3 lpc1758_56_54_52_51 v.3 20091119 product data sheet - lpc1758_56_54_52_51 v.2 lpc1758_56_54_52_51 v.2 20090211 objective data sheet - lpc1758_56_54_52_51 v.1 lpc1758_56_54_52_51 v.1 20090115 objective data sheet - -
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 71 of 74 nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. 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the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? 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lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 72 of 74 continued >> nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc1759_58_56_54_52_51 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights res erved. product data sheet rev. 7 ? 29 march 2011 73 of 74 continued >> nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 4 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 functional description . . . . . . . . . . . . . . . . . . 13 7.1 architectural overview . . . . . . . . . . . . . . . . . . 13 7.2 arm cortex-m3 processor . . . . . . . . . . . . . . . 13 7.3 on-chip flash program memo ry . . . . . . . . . . . 13 7.4 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 13 7.5 memory protection unit (mpu). . . . . . . . . . . . 13 7.6 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.7 nested vectored interrupt controller (nvic) . 16 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.7.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 16 7.8 pin connect block . . . . . . . . . . . . . . . . . . . . . . 16 7.9 general purpose dma controller . . . . . . . . . . 16 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.10 fast general purpose parallel i/o . . . . . . . . . . 17 7.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.11 ethernet (lpc1758 only) . . . . . . . . . . . . . . . . 18 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.12 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.12.1 usb device controller . . . . . . . . . . . . . . . . . . . 19 7.12.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.12.2 usb host controller (lpc1759/58/56/54 only). 20 7.12.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12.3 usb otg controller (lpc1759/58/56/54 only).. . . . . . . . . . . . . . . . 20 7.12.3.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.13 can controller and acceptance filters . . . . . . 20 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14 12-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.15 10-bit dac (lpc1759/58/56/54 only) . . . . . . . 21 7.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16 uarts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.17 spi serial i/o controller. . . . . . . . . . . . . . . . . . 22 7.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.18 ssp serial i/o controller . . . . . . . . . . . . . . . . . 22 7.18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.19 i 2 c-bus serial i/o controllers. . . . . . . . . . . . . . 23 7.19.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.20 i 2 s-bus serial i/o controllers (lpc1759/58/56 only) . . . . . . . . . . . . . . . . . . 23 7.20.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.21 general purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 24 7.21.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.22 pulse width modulator . . . . . . . . . . . . . . . . . . 25 7.22.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.23 motor control pwm . . . . . . . . . . . . . . . . . . . . 26 7.24 quadrature encoder inte rface (qei) . . . . . . . 26 7.24.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.25 repetitive interrupt (ri) timer. . . . . . . . . . . . . 27 7.25.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.26 arm cortex-m3 system tick timer . . . . . . . . . 27 7.27 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 27 7.27.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.28 rtc and backup registers . . . . . . . . . . . . . . . 28 7.28.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.29 clocking and power control . . . . . . . . . . . . . . 28 7.29.1 crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 28 7.29.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 29 7.29.1.2 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 29 7.29.1.3 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 29 7.29.2 main pll (pll0) . . . . . . . . . . . . . . . . . . . . . . 30 7.29.3 usb pll (pll1) . . . . . . . . . . . . . . . . . . . . . . 30 7.29.4 wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 30 7.29.5 power control . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.29.5.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.29.5.2 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 31 7.29.5.3 power-down mode . . . . . . . . . . . . . . . . . . . . . 32 7.29.5.4 deep power-down mode . . . . . . . . . . . . . . . . 32 7.29.5.5 wakeup interrupt controller . . . . . . . . . . . . . . 32 7.29.6 peripheral power control . . . . . . . . . . . . . . . . 32 7.29.7 power domains . . . . . . . . . . . . . . . . . . . . . . . 32 7.30 system control . . . . . . . . . . . . . . . . . . . . . . . . 34 7.30.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.30.2 brownout detection . . . . . . . . . . . . . . . . . . . . 35 7.30.3 code security (code read protection - crp) 35 7.30.4 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.30.5 ahb multilayer matrix . . . . . . . . . . . . . . . . . . 36 7.30.6 external interr upt inputs . . . . . . . . . . . . . . . . . 36 7.30.7 memory mapping control . . . . . . . . . . . . . . . . 36 7.31 emulation and debugging . . . . . . . . . . . . . . . 36 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 37 9 thermal characteristics . . . . . . . . . . . . . . . . . 38 9.1 thermal characteristics . . . . . . . . . . . . . . . . . 38
nxp semiconductors lpc1759/58/56/54/52/51 32-bit arm cortex-m3 microcontroller ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 29 march 2011 document identifier: lpc1759_58_56_54_52_51 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 10 static characteristics. . . . . . . . . . . . . . . . . . . . 39 10.1 power consumption . . . . . . . . . . . . . . . . . . . . 42 10.2 peripheral power consumpt ion . . . . . . . . . . . . 45 10.3 electrical pin characteristics . . . . . . . . . . . . . . 46 11 dynamic characteristics . . . . . . . . . . . . . . . . . 48 11.1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.3 internal oscillators. . . . . . . . . . . . . . . . . . . . . . 49 11.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.5 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.6 i 2 s-bus interface (lpc1759/58/56 only) . . . . . 52 11.7 ssp interface . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.8 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.9 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12 adc electrical characteristics . . . . . . . . . . . . 58 13 dac electrical characteristics (lpc1759/58/56/54 only) . . . . . . . . . . . . . . . . . 61 14 application information. . . . . . . . . . . . . . . . . . 62 14.1 suggested usb interface solutions . . . . . . . . 62 14.2 crystal oscillator xtal input and component selection. . . . . . . . . . . . . . . . . . . . 64 14.3 xtal printed-circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14.4 standard i/o pin configuration . . . . . . . . . . . . 66 14.5 reset pin configuration . . . . . . . . . . . . . . . . . . 67 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 68 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 69 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 70 18 legal information. . . . . . . . . . . . . . . . . . . . . . . 71 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 71 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 18.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 72 19 contact information. . . . . . . . . . . . . . . . . . . . . 72 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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